The conventional circuit of a cell of a static random access memory (SRAM) device is well known. It has two access transistors, two driver transistors (also known as "pull-down" transistors), and two load elements.
Three types of load elements are typically used in the conventional SRAM cell. These are: i) a depletion-type NMOS transistor; ii) a high-resistance polysilicon; or iii) a PMOS transistor.
The SRAM devices constructed of a CMOS process typically have PMOS transistor load elements. The PMOS load element provides for a memory device with low standby current and power consumption. However, the use of a PMOS transistor as the load element significantly enlarges the two-dimensional area required by a single SRAM memory cell, because of the formation of six transistors in the cell.
A conventional CMOS SRAM cell with PMOS transistor load elements comprises two NMOS access transistors, two NMOS driver transistors, and two PMOS transistors formed together on a semiconductor substrate.
The conventional CMOS SRAM cell with high-resistance polysilicon load elements has only four transistors formed for each cell. The high-resistance polysilicon load element is conventionally formed above the two NMOS access and two NMOS driver transistors.
Conventional SRAM cells have also been formed with two PMOS thin film transistors (TFT) as load elements laid over the conventional structure of two NMOS access and two NMOS driver transistors. The conventional layout of the two access and two driver transistors is illustrated in FIG. 1. However, the conventional PMOS TFT structure does not reduce the required area of an SRAM cell beyond that which was required by the SRAM device which uses high-resistance polysilicon load elements.
A CMOS SRAM memory cell using PMOS TFT load elements is illustrated in an NEC paper by H. Ohkubo et al. in IEDM '91 entitled "16 Mbit SRAM Cell Technologies for 2.0 V Operation". In this paper, an insulating film is deposited to form the PMOS TFT load elements within the area occupied by the access and driver transistors, but the use of the PMOS TFT does not reduce the required area of the conventional SRAM memory cell. A reduction in the area of each cell is required to achieve a higher integration of memory in a single device.
FIG. 1 illustrates the layout of the access and driver transistors of a conventional SRAM cell, such as in the Ohkubo paper and a Fujitsu paper by Kazuo Itabashi et al., in IEDM '91, entitled "A Split Wordline Cell for 16 Mb SRAM Using Polysilicon Sidewall Contacts". The SRAM cell comprises two word lines forming the gates of the access transistors, and the gates of the driver transistors and word lines are formed from the same layer.
A more complicated structure of an SRAM cell was by A. O. Adan et al. at the 1990 Symposium on VLSI Technology, in a paper entitled "A Half-micron SRAM Cell Using a Double-gated Self-aligned Polysilicon PMOS Thin Film Transistor (TFT) Load". In Adan's paper, the gates of the two access transistors are formed with a single word line. However, this more complicated structure has disadvantageous features, such as a higher amount of bird's beak into the active regions, ultimately resulting in a less reliable device.
There are two word lines which interconnect the memory cells in a conventional SRAM device, both serially connected to adjacent memory cells. The gates of the driver transistors, the gates of the access transistors, and the word lines are all formed by patterning the same conductive layer. Because the gates of the driver transistors are located on the same layer but between the word lines, the minimum area of the memory cell is dictated by the minimum size of these common layer components.
Therefore, because the word line is formed from the same layer as the gate of the driver transistor, it is difficult to achieve further significant reductions in the size of the memory cell with the structure of the conventionally known SRAM device.